12/3 Algorithm-Hardware Co-Design for Machine Learning (박종세 교수/KAIST 전산학부)

작성자
kaistsoftware
작성일
2020-12-01 16:28
조회
13323
  • 강사 : 박종세 교수 (KAIST 전산학부)  
  • 일시 : 2020. 12. 3 (목) 17:00~18:30
As the computational demand of emerging applications (e.g., deep learning) rapidly increases, the benefits of conventional general-purpose solutions are diminishing. Acceleration has been a promising alternative solution that delivers orders-of-magnitude higher performance and energy efficiency gains compared to the general-purpose counterparts. However, achieving both performance and programmability at the same time is still the greatest challenge to facilitate the use of such acceleration solutions. I will talk about two works that address this challenge by developing hardware-software co-designed full stack solutions. I will first talk about Bit Fusion, a novel DNN acceleration solution, which leverages the inherent algorithmic properties of DNNs and provides a bit-flexible accelerator that dynamically fuse the on-chip computing units to match the bit width of individual DNN layers. I will then talk about INCEPTIONN, a hardware-algorithm co-designed in-network acceleration solution for distributed DNN training system, which significantly reduces the inter-node communication overhead and in turn substantially improves the end-to-end DNN training performance.
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